Low-Power Techniques for FPGA and ASIC Design: A Comprehensive Survey

Power efficiency has emerged as a significant constraint in the design of modern digital systems, requiring a holistic approach that includes architectural, register-transfer level, and physical implementation stages. This survey comprehensively reviews low-power design techniques for FPGA and ASIC technologies developed in the last five years. It addresses high-level synthesis optimizations, RTL power-aware methodologies, and dynamic power management techniques, including clock gating, power gating, and voltage scaling. The backend activities discussed in the paper are power-driven placement, multi-threshold and multi-voltage design, leakage minimization, and robust power grid architectures. The quantitative trends in junction scaling and process technology, such as FinFET and GAA transistors, are elaborated along with emerging paradigms of chipset-based integration and machine learning-driven design automation. It also addresses application-specific low-power techniques for application domains such as IoT, AI accelerators, and high-performance computing. The paper ends with directions toward adaptive, context-aware systems that minimize real-time power consumption (given the workload and changing conditions). This work presents a coherent reference for designers, researchers, and engineers to comprehend cutting-edge low-power design methodologies through a unified consolidation of the scientific and industrial body of knowledge.