Design Analysis of a Modified Current Reuse Low Power Wideband Single-Ended CMOS LNA

This paper presents the design analysis of a low power wideband single-ended CMOS low-noise amplifier (LNA). The proposed topology is based on the modified current reuse circuit to achieve good performance and low power consumption. Two stage current source (CS) amplifiers consume the same DC current which are isolated with large MIMCAPs. The proposed circuit has 2.5 GHz bandwidth which can cover several wireless communication standards (GSM, WLAN and Bluetooth). In first stage a current reuse circuit with shunt feedback is used to satisfy input impedance matching and amplify the signal with minimal noise injection. A common source (CS) with a source follower circuit forms the second stage to improve NF, harmonic distortion and also output impedance matching. The proposed LNA is designed in 65-nm CMOS technology with 2.51 GHz bandwidth that covers frequency range of 0.17-2.68 GHz. The post-layout simulation results show a maximum S21 of 17.24 dB, minimum NF of 2.67 dB, maximum IIP3 of -14.9 dBm, input and output return losses less (S11, S22) than -10 dB while power consumption is 3.52 mW from 1 V power supply. Excluding pads, the proposed circuit occupies 0.45 mm2 silicon die area.