The Heterojunction Gate-All-Around Spintronic Tunnel FET (HG-Spin-TFET): A Pathway to Multifunctional, Ultra-Low-Power Nanoelectronics

The relentless scaling of conventional CMOS technology is confronting a fundamental power wall, driven by the thermal limits of thermionic emission in MOSFETs. This paper addresses this challenge by proposing a novel device architecture: the Heterojunction Gate-All-Around Spintronic Tunnel Field Effect Transistor (HG-Spin-TFET). This device is designed to overcome the inherent trade-offs of existing beyond-CMOS solutions by synergistically integrating four key technologies. First, it leverages the quantum mechanical band-to-band tunneling (BTBT) mechanism of a TFET to break the 60 mV/decade subthreshold swing (SS) limit. Second, it employs a Gate-All Around (GAA) nanowire architecture for ultimate electrostatic control, maximizing switching efficiency. Third, it incorporates a III-V/2D material heterojunction (InAs/MoS2) at the source to dramatically enhance the tunneling probability, addressing the TFET’s traditional low ON-current (ION) limitation. Fourth, it integrates ferromagnetic source/drain contacts to utilize electron spin, adding non-volatile memory functionality through the Tunnel Magnetoresistance (TMR) effect. Theoretical modeling and performance projections suggest the HG-Spin-TFET can achieve an average SS below 20 mV/decade, an ION/IOFF ratio exceeding 1010, and a TMR greater than 300% at room temperature. This combination of ultra-low-power switching and embedded memory positions the HG-Spin-TFET not merely as a superior transistor, but as a foundational component for future in-memory computing and reconfigurable logic architectures, offering a potential route to bypass the von Neumann bottleneck at the device level.