Microprocessor-Based FPGA Architectures for Fast Image Compression Algorithms

This paper investigates microprocessor-based FPGA and FPSoC architectures for real-time image compression, focusing on three representative encoders: JPEG, JPEG2000, and the non-embedded LTW wavelet encoder. Following a hardware/software co-design methodology, we implement and evaluate multiple architectural alternatives that combine embedded soft processors with dedicated coprocessors to accelerate key stages of the compression pipeline. The proposed designs are compared in terms of rate–distortion performance, coding latency, power dissipation, and occupied board area, highlighting the trade-offs between flexibility and throughput. Experimental results show that a dual MicroBlaze configuration augmented with a DWT coprocessor for LTW achieves throughputs up to 13.7 Msamples/s while maintaining compression efficiency comparable to JPEG2000. These findings provide practical guidance for selecting FPGA-based compression architectures under stringent real-time constraints in applications such as video surveillance, medical imaging, and high-speed cameras.