Programmable Zero-Power Silicon Photonic Read-Only Memory and Compute In-Memory Circuits

Wide adoption of optical computing systems necessitates the use of integrated photonic platforms that can synergize non-volatile long-term information storage with efficient linear operation architectures. Non-volatile optical memory operation is emerging as a next generation compute system enabler, as this can support high-speed yet zero electrical power for traditional Read-Only-Memory (ROM) deployments required by firmware, boot procedures and lookup tables. At the same time, this enables a diverse range of compute-in-memory (CIM) edge inference tasks that rely on fixed or rarely updated model parameters, provided that non-volatile memory allows also for analog operation and gets combined with optimized linear optical circuit architectures. In this work, we report the first fully CMOS-compatible silicon photonic programmable read-only memory (SiPROM) and combine this with different architectural schemes to demonstrate experimentally a 36 bit zero-power digital SiPROM bank, a coherent analog 4x9 CIM unit, and a 2-bit 9-word zero-power 50 Gb/s content-addressable memory (CAM) bank. The SiPROM memory cell comprises an n-rich SiNx-based Mach–Zehnder interferometer (MZI) with its memory state being programmed through controlled waveguide refractive index modifications caused by ultraviolet (UV) beam exposure, enabling in this way zero-power non-volatile storage without electrical biasing, thermal tuning, or the use of exotic materials. We demonstrate a zero-power digital SiPROM bank by utilizing this memory cell technology within a matrix arrangement, with its functionality being elevated to an analog coherent CIM circuit and a high-speed CAM bank when the matrix arrangement gets combined with linear optical circuit architectures. We believe that the fully CMOS compatible nature of this SiPROM technology together with its successful demonstration across a range of scaled-up digital and analog system-scale functions can pave the way towards high-speed and zero-power memory and compute operations required by critical communications and edge AI segments.