An Embedded High-Order Runge–Kutta 6(5) Pair with Adaptive Step Control for Low- Latency Real-Time Signal Processing on Resource-Constrained Platforms

Real-time signal processing on small embedded devices often depends on solving ordinary differential equations to model dynamic behavior in audio effects, sensor data fusion, and control loops. Fixed-step low-order Runge-Kutta solvers like RK4 give predictable timing but require very small steps on problems with mixed fast and slow dynamics, which wastes cycles and raises power use. Higher-order adaptive methods can adjust the step size automatically for better efficiency, but their extra stages and variable timing make them hard to run on low-power microcontrollers or small FPGAs without breaking latency guarantees. This work describes a practical 6(5) embedded Runge-Kutta pair with bounded step-size adaptation designed specifically for such constrained hardware. The implementation uses a compact eight-stage Verner coefficient set that supports FSAL and dense output, fixed-point arithmetic with careful stage reuse, and a simple controller that limits step changes while adding hysteresis to keep execution time within known bounds. Tests on an STM32F407 microcontroller and an Artix-7 FPGA covered a stiff Van der Pol oscillator, a nonlinear diode ladder filter, and an extended Kalman filter for inertial sensors. Compared to fixed RK4 and a bounded Dormand-Prince 5(4) variant, the new solver cut global errors by more than an order of magnitude for similar average latency, kept worst-case latency suitable for sampled loops, and often used less energy on varying workloads. Step rejections stayed below 8% in all cases. The results show that a tuned high-order adaptive solver can run reliably on severely limited platforms, allowing richer dynamic models in battery-powered edge applications without losing real-time predictability.