Constraint-Aware Circuit-Level DAG Generation Using Full-Topology Enumeration

Directed Acyclic Graphs (DAGs) serve as fundamen tal structural representations for combinational logic circuits, data flow graphs, and Boolean dependency networks. In recent years, the rapid application of machine learning (ML) techniques in logic synthesis, satisfiability (SAT) solving, and hardware secu rity has generated a strong demand for large-scale, structurally diverse circuit netlist datasets. However, existing circuit gener ators either suffer from insufficient diversity when rule-based or exhibit poor structural controllability and low topological space coverage when random-based. This paper proposes a fast and accurate random circuit netlist generator based on DAG theory and full topological enumeration principles. Inspired by the FT-DAG framework, this generator combines shape-driven DAGconstruction with circuit-specific constraints, including fixed input scale, precise internal fan-in, and controllable number of sink nodes. The framework addresses combinatorial explosion in the graph space through a hierarchical search strategy. Experimental results demonstrate high structural diversity, strict constraint satisfaction, and scalability, making it an ideal choice for data-intensive AI-driven EDA workflows.