Study on the Effect of Polishing Pad Layer Structure on Dishing Control in Chemical Mechanical Planarization of Through-Silicon Via Copper Patterned Wafer

In advanced semiconductor manufacturing, copper interconnects fabricated via the dual damascene process rely heavily on chemical mechanical planarization (CMP) to achieve global planarity and defect-free surfaces. However, achieving optimal material removal uniformity, minimal dishing in recessed features, and low surface roughness remains challenging for through-silicon via copper structure on patterned wafers. Addressing these issues, this study developed a novel in-situ downforce simulation apparatus combined with the quadrat method for asperity spatial analysis to elucidate the role of polishing pad layer architecture in CMP performance. Multi-scale nano-indentation and real-time contact imaging were employed to compare the monolithic IC1000 polishing pad with the bilayer ICSU polishing pad. Results revealed that the ICSU polishing pad, owing to its compliant Suba™ IV sub-layer, exhibits greater asperity deformability, higher real contact area ratio, and more uniform asperity distribution under various downforce. Consequently, the ICSU polishing pad delivered superior CMP surface roughness and within-wafer uniformity, whereas the stiffer IC1000 polishing pad provided better dishing control in patterned features. These findings highlight fundamental trade-offs in polishing pad design and offer practical guidance for polishing pad selection in high-density copper interconnect CMP process, with potential to enhance yield and reliability in next-generation devices.