Explainable Machine Learning Framework for RTL Timing Prediction: Bridging the Gap Between Black-Box AI and Hardware Design

In modern VLSI design, achieving timing closure is a critical and time-consuming bottleneck. Tradi- tional Static Timing Analysis (STA) tools are ac- curate but computationally expensive, often requir- ing hours or days for full chip analysis. This de- lay hinders rapid design exploration at the Register- Transfer Level (RTL). While Machine Learning (ML) models have shown promise, they often suffer from the “Black Box” problem. Here, we present a dual- phase framework integrating Graph Neural Networks (GNNs) with eXplainable AI (XAI) to achieve ac- celerated and transparent timing closure. By repre- senting circuit topology via the Graph Laplacian and modeling thermal dissipation as a diffusive process, our model achieves a 74.4% error reduction over base- line statistical models and enables Zero-Shot Trans- fer Learning