Benchmarking SLH-DSA: A Comparative Hardware Analysis Against Classical Digital Signatures for Post-Quantum Security

The imminent threat posed by large-scale quantum computers necessitates a paradigm shift from classical public-key cryptography to quantum-resistant solutions. In response, the National Institute of Standards and Technology (NIST) has stan- dardized several Post-Quantum Cryptography (PQC) algorithms, including the Stateless Hash-Based Digital Signature Algorithm (SLH-DSA), specified in FIPS 205. The practical adoption of SLH-DSA, particularly in hardware-constrained environments such as embedded systems and Root-of-Trust (RoT) modules, depends critically on a comprehensive understanding of its performance and resource overhead relative to legacy standards. This paper presents a definitive hardware benchmarking study, implementing and synthesizing Verilog HDL designs for SLH- DSA and a suite of classical signature schemes—RSA, DSA, ECDSA, and EdDSA—on a unified Xilinx FPGA platform. Our comparative analysis focuses on key hardware metrics: resource utilization (LUTs, FFs, BRAMs, DSPs) and performance charac- teristics (latency for key generation, signing, and verification; and overall throughput). The results quantify the significant trade-offs inherent in SLH-DSA; it exhibits substantially higher signing latency and produces larger signatures than its classical counterparts. However, its verification performance is highly competitive, and its security is conservatively based on well- understood hash functions. The hardware architecture of SLH- DSA is logic- and memory-intensive, contrasting sharply with the DSP-heavy nature of RSA and ECC. We conclude that while SLH-DSA presents a computationally expensive option, its robust security model makes it a viable solution for applications prioritizing long-term security assurance over raw signing performance, such as firmware signing and digital archiving.