AI Enabled Low Power UART Architecture Optimization with CMOS 130nm PDK Technology for Automobile Applications

This work presents an AI-enabled low-power UART (Universal Asynchronous Receiver Transmitter) architecture optimized for advanced automotive applications using a hybrid front-end and back-end design approach. The front-end design and functional verification are carried out in Vivado, while the back-end physical implementation and power optimization are performed using the Sky Water 130 nm PDK technology. The proposed design integrates artificial intelligence–based optimization strategies to enhance communication efficiency and minimize total power dissipation. Machine learning techniques, including reinforcement learning and regression-based prediction, are employed to analyse switching activity and workload behaviour, enabling real-time adaptive control of key operating parameters such as voltage, frequency, and clock gating. By incorporating dynamic voltage and frequency scaling (DVFS) and adaptive clock gating, the architecture achieves notable reductions in both dynamic and static power while maintaining high data integrity. The AI-assisted UART intelligently manages buffer utilization and module activation based on data traffic patterns, leading to superior energy efficiency and performance balance. Simulation and physical verification demonstrate significant improvements in power, latency, and area compared to conventional UART architectures. The proposed architecture provides a scalable, energy-efficient, and intelligent communication interface, ideally suited for next-generation automotive embedded and sensor systems requiring low power and high reliability.