Local Scrambling and Structural Gradient Bias in Hardware-Efficient Quantum Circuits

Barren plateaus (BPs) are often considered a fundamental barrier to training variational quantum algorithms, since gradient magnitudes may vanish exponentially with system size or circuit depth. We show that even when gradients remain non‑zero, standard hardware‑efficient ansätze can suffer a distinct \emph{structural} pathology: a commutativity‑induced bottleneck that confines gradient signal near the cost support while effectively freezing distant qubits. To mitigate this, we propose a minimal “local‑scrambling” modification of the ubiquitous $R_Y$–$R_Z$ + $CZ$ brickwork circuit. By inserting small $X$‑rotation blocks on selected bonds, the cost’s $Z$ operators are locally converted into non‑commuting components, enhancing operator spreading in a geometry‑aware manner while preserving the full dynamical Lie algebra. We validate this idea using spatial gradient diagnostics — center–edge bias, per‑qubit gradient entropy, and bond‑resolved learning trajectories — in noiseless state‑vector simulations up to $N = 16$ qubits, plus a simple 2‑design–inspired toy model. For a global observable, local scrambling leaves the exponential BP scaling intact, causing only a modest constant‑factor change. In contrast, for multi‑local Ising‑type costs, appropriately placed scramblers redistribute gradient energy, modestly reduce the center–edge bias, and increase gradient entropy within a finite light cone. Density‑variation experiments reveal that these gains are constrained by a finite operator‑spreading length: increasing scrambler density mainly reshapes anisotropy into multiple hot spots. Overall, our results expose an explicit “performance–fairness” trade‑off in hardware‑efficient ansätze and establish local scrambling as a minimal, geometry‑aware design principle for reshaping — rather than eliminating — gradient anisotropies in the NISQ regime.