A Low-Power CMOS Spiking Neuron Design with Frequency Adaptation in 180nm Technology at 300mV Supply

This paper presents a low-power spiking neuron design using 180 nm CMOS technology, operating at a 300 mV supply with a frequency adaptation mechanism. The design achieves an energy consumption of 9.3 pJ/spike, a 22.5% improvement over the baseline model (12 pJ/spike), a stable 255 Hz firing frequency, and a 70% increase in spike amplitude through a P-type transistor in the feedback loop. Simulations in ADS confirm the design’s stability, though the lack of hardware validation remains a limitation. Compared to advanced nodes (e.g., 28 nm), it offers a cost-effective solution for IoT and robotics applications, with potential memristor integration enhancing synaptic flexibility. Future work includes hardware validation and scalability improvements.