Hardware Software Codesigned Accelerator for CRYSTALS-Kyber Using a RISC-V Vector Processor

This study introduces a hardware/software co-design CRYSTALS-Kyber accelerator implemented on a field-programmable gate array (FPGA) using a RISC-V-based vector co-processor. The design optimizes multiplication operations to enhance resource efficiency and explores the implementation of high-speed CRYSTALS-Kyber using a Single Instruction Multiple Data (SIMD) approach. Implemented on the FPGA, the design utilizes 8,407 flip-flops, 14,783 look-up tables, 45 block random access memories, and six digital signal processing blocks, achieving a maximum operating frequency of 134.616 MHz. We employed parallelization and loop unrolling, achieving a balance between resource utilization and computational speed. We determined that numerous cores can be implemented on Kyber's processing unit in the hardware to accelerate lattice-based post-quantum cryptography.