Low Power and Highly Stable 10T SRAM Cell Design Using Stacked and MTCMOS Techniques

A comparison of three 10T SRAM designs, Conventional, Stacked and Multi-Threshold CMOS (MTCMOS) was conducted at the 90 nm technology node. This followed earlier findings that the 10T SRAM out performed the 6T, 8T and 12T designs. The 10T cell was chosen for its optimal balance of power use, stability, and performance. It achieved a higher static noise margin (SNM) and significantly lower power consumption than the 8T and 12T designs. The three variations of 10T implementations were then closely compared, revealing that the MTCMOS-based 10T SRAM cell out performed the other two. The simulation results showed that the 10T SRAM based on MTCMOS was the most stable, with a Static Noise Margin (SNM) of 379.456 mV. It also had the lowest power consumption at 13.8 μW. At the process corners, SRAM cells achieved the best average voltage and stability in FF. There was minimal degradation in FS and FF-like behaviour in SF, while the worst case occurred at SS. For leakage, the MTCMOS 10T had the lowest value, around 720 μW. Although the stacked 10T SRAM showed better read/write performance and output quality, it did not match the MTCMOS scheme in static power reduction. In general, the 10T SRAM cell based on MTCMOS is the most stable and energy-efficient option for future high-performance,low-power applications.