Novel Submicron Sheet Fully-Enclosed Gate-Drift SOI LDMOS Achieving Ultra-Low RON,sp

A lateral double-diffused MOSFET based on silicon-on-insulator technology with submicron sheet fully-enclosed gate and drift structures (FEGD-LDMOS) is proposed and investigated. The fully-enclosed gate (FEG) architecture maximizes effective channel width utilization, significantly reducing channel resistance while enhancing gate control over charge carriers. Meanwhile, the ON-resistance in the drift is significantly reduced, as the proposed FEGD device incorporates a fully-enclosed drift (FED) region that completely surrounds the drift and introduces a 3D completely enclosed electron accumulation layer (EAL) in the drift region. Moreover, a control electrode integrated atop the FED region deftly modulates the strength of the EAL to achieve the optimal accumulation effect, which reduces the ON-state power consumption. Consequently, the FEGD device allows synergistic optimization of drift and channel resistances, achieving an ultra-low specific ON-resistance (\((R_{ON,sp})\)) . Simulation results indicated that the \((R_{ON,sp})\) of FEGD-LDMOS was reduced from 14.18 \((\text{m}\Omega \cdot \text{cm}^2)\) for the conventional planar LDMOS (Cov. LDMOS) to 0.14 \((\text{m}\Omega \cdot \text{cm}^2)\), representing a remarkable reduction of 99.0% at the same breakdown voltage ( BV ) of 190 V. The Figure-of-merit ( FOM ) of the FEGD-LDMOS increased from 2.8 MW/\((\text{cm}^2)\) for the Cov. LDMOS to an extremely-high 269.1 MW/\((\text{cm}^2)\), demonstrating exceptional performance.