General Principles for Implementing Branch Prediction in Fully Adiabatic, Reversible, and SuperScalar (FARS) Processors

Adiabatic and reversible logic families take advantage of Landauer's principle to provide a more efficient means of computation using conventional MOSFETs. However, there are performance drawbacks inherent in the way such devices physically operate. Such drawbacks can be overcome by scaling the number of devices to meet performance needs. In previous work, we proposed that implementing superscalar out-of-order techniques in the micro-architecture of a fully adiabatic and reversible processor would further boost the performance and reduce the number of parallel units in such a system. In that work, we introduced a few first-of-their-kind reversible branch predictors that enabled what we are calling Fully Adiabatic, Reversible, and Superscalar (FARS) Processors. Our work represents a unique contribution, providing the first instances of reversible principles applied to advanced computer architectures. By focusing on reversibility at the micro-architecture level, we estimate recapturing upwards of 57.1 nJ per MB of obsolete SRAM data when implemented with existing reversible logic families. Here, we expand on that with several more reversible branch predictors and the inclusion of general principles for designing and implementing such hardware in a FARS system. With these new predictors, we show an improvement in the branch prediction hit rate in the reverse mode of up to 3.39\% over the forward mode. This is on top of the already inherent performance boosts seen from executing out-of-order. Our work is the first in a series that establishes general principles for adapting superscalar hardware to a fully adiabatic and reversible system.