Scalable Optical MIMO processor using Silicon Photonics

Next generation wireless communications systems are rapidly penetrating higher RF frequency bands together with massive Multiple-Input-Multiple-Output (MIMO) communication schemes, requiring processing units to perform at millimeter-wave RF carriers while supporting high-bandwidth and highly scalable configurations. However, operating electronic MIMO processing units at such high-frequency and high-bandwidth system requirements becomes extremely challenging when targeting beneficial energy consumption metrics. Photonic processors emerge as a promising alternative to tackle channel interference encountered in MIMO systems, with the main argumentation building on the large available bandwidth and favorable energy efficiency credentials of Photonic Integrated Circuit (PIC) technologies. However, photonic MIMO processors that support more than 2 channels are currently entirely missing; moreover, their architectural framework relies exclusively on matrix decomposition algebra, raising significant concerns about their scalability potential. In this paper, we present a scalable silicon photonic (SiPho) MIMO processor architecture that exploits the coherent crossbar (Xbar) interferometric layout and demonstrates experimentally its successful performance in proof-of-concept MIMO setups. The zero-forcing photonic processor can cancel channel interference and compensate for phase offsets in the received signals. The experimental validation of the proposed system is performed through a 4×4 SiPho Xbar chip, demonstrating 3×3 and 4×4 MIMO processing with phase offset compensation capabilities for both single-tone and data-modulated RF channels, transmitted through arbitrary linear channels. This work presents, to the best of our knowledge, the largest demonstrated photonic MIMO processor, utilizing the SiPho Xbar linear optical circuit architecture and bearing the promise of scaling to more than 32 high-RF frequency and mmWave wireless channels.