CMOS-Compatible FTJ Hardware Unifying Stochastic Sampling and Deterministic Computing for On-Chip Image Generation

Recent progress in generative modeling has intensified the need for compact, energy-efficient hardware platforms. Yet, implementing image generation directly in hardware remains challenging due to the conflicting requirements of stochastic latent-space sampling and deterministic decoding. Here, we present a unified hardware framework based on hafnium-oxide ferroelectric tunnel junctions (FTJs) that intrinsically support both functionalities within a single device array. Leveraging the CMOS- and VLSI-compatible fabrication of hafnia ferroelectrics, we realize dual-mode operation: random telegraph noise generation for controllable stochastic sampling, and high-fidelity vector–matrix multiplication enabled by non-volatile multi-level conductance states. Voltage and sampling-time tuning provide fine control over randomness and reliability, enabling high-quality image generation for tasks such as handwritten digit synthesis (MNIST) and high-resolution facial image generation (CelebA). Circuit-level demonstrations confirm stable performance over 10 ⁵ cycles, surpassing prior hardware-based approaches and illustrating a viable route toward scalable, on-chip generative AI accelerators.