Adaptive Arbitration Mechanisms for Heterogeneous NoCs under Diverse Load Scenarios

Modern heterogeneous multi-core chips are increasingly integrating diverse types of computing units to enhance system performance, among which CPUs and GPUs exhibit significant differences in communication patterns and resource demands. These differences pose new challenges to on-chip networks (NoCs) in task scheduling and resource allocation. Efficiently coordinating resources among various computation tasks to maintain communication performance under dynamic loads has become a key issue in system design. To address this challenge, this paper proposes three adaptive arbitration mechanisms for heterogeneous NoCs, each tailored to different load scenarios. These mechanisms are respectively designed based on task-aware time-slice allocation, port load feedback adjustment, and reinforcement learning-driven dynamic arbitration. Simulation experiments on a heterogeneous platform demonstrate that the proposed methods exhibit significant advantages across different application scenarios. Notably, under high-load conditions, the RATS mechanism reduces average network latency by 40.4% and improves CPU performance by 14.2%.