Sustainable Chemical Mechanical Planarization Optimization for Copper Thin Film Wafer with Multi-Objective Optimization Approach

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Abstract

Chemical mechanical planarization (CMP) of copper-coated thin film on silicon wafers plays a pivotal role in semiconductor manufacturing for ensuring micronscale wafer flatness and nanoscale surface roughness. However, semiconductor manufacturing is very energy-consuming and also not so environmentally friendly. With increasing emphasis on environmental sustainability, monitoring energy saving, which relates to tracking carbon footprints, has become integral to advancing manufacturing technologies, especially for semiconductor manufacturing. This study presents a structured and efficient framework to reduce energy consumption in the CMP process using a multi-objective optimization (MOO) approach. Sought to minimize energy consumption by maximizing the material removal rate (MRR) and minimizing surface roughness, a hybrid two-stage optimization framework, which integrates Nondominated sorting genetic algorithm II (NSGA-II) and Analytic hierarchy process (AHP), has been proposed to achieve the objective. The model leverages real-world experimental data, which are practically collected by a custom-implemented platform on-site data acquisition system during the CMP process of copper thin film wafers. Through parameter optimization, the hybrid framework enables the identification of optimal operating conditions. While the NSGA-II produces a Pareto front with multiple optimal feasible solutions, a modified quasi-AHP method is devised to rank these solutions successively and finalize an effectively informed decision-making model. As a result, an optimized parameter combination for efficient CMP operation has been computationally identified, coherent with the experimental outcomes. Although the model dwells at a prototype scale, the theoretical rigor and experimental consistency of the proposed NSGA-II–quasi-AHP (NIIqA) framework reveals its promising applicability to broader CMP process optimization and sustainable semiconductor manufacturing practices.

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