Hardware Trojan Localization with Minimal False Negative in Gate- Level Netlists using Graph Encoding Embedded Neural Network Approach

Hardware Trojans (HTs) pose a severe threat to the security and reliability of integrated circuits (ICs), necessitating advanced detection mechanisms beyond traditional verification and testing approaches. The proposed work presents a graph-based machine learning framework that integrates a graph encoder at preprocessing stage to enhance the feature extraction process for HT detection in gate-level netlists. The methodology leverages Graph Neural Networks (GNNs) for both (a) graph-level classification, which differentiates between Trojan-infected and non-infected circuits and (b) node-level classification which precisely locates malicious gate-level modifications. The graph encoder plays an important role in transforming the netlist into a structured, high-dimensional feature space, capturing intricate interdependencies between circuit components. By refining the representation of logic gates and their connectivity, the encoder enables the model to learn subtle structural patterns indicative of HT insertions. Experimental results on benchmark gate-level netlists demonstrate that integrating a graph encoder enhances classification accuracy, with graph-based detection improving from 62.8–82% and node-level detection from 79.8–86.2% for a large dataset considered in the present study. Further, utilizing first nearest neighbour-based detection shows improvement from 62.8–86.6% and node-level detection utilizing first nearest neighbour shows improvement from 79.8–95.5%. Second nearest neighbour shows accuracy of 98.3% for both the graph-based and node-based detection techniques. The findings validate the proposed approach in accurately localizing HT with minimal false negatives, offering a scalable and robust solution for secure integrated circuit design.