Optimizing SIMON 64/128 on Artix-7 FPGA: A Comparative Analysis of Loop Unrolling and Pipelining Trade-offs

The rapid expansion of Internet of Things (IoT) devices demands lightweight cryptographic solutions that balance security, throughput, resource utilization, and power efficiency in resource-constrained environments. The SIMON 64/128 block cipher, with its compact Feistel structure, is well-suited for FPGA-based IoT applications but requires optimized architectures to meet diverse performance requirements. Prior studies often focus on limited configurations, such as low-degree loop unrolling or coarse-grained pipelining, leaving a gap in systematic architectural comparisons. This study comprehensively evaluates SIMON 64/128 architectures--iterative, loop-unrolled (factors 2 to 44), and pipelined (4-, 2-, and 1-round stages)--on the Artix-7 FPGA, addressing the lack of systematic architectural comparisons in prior work. Results demonstrate that loop unrolling increases throughput linearly up to a factor of 16 (1.13~Gbps), beyond which resource and power costs escalate significantly, with factor-44 consuming 0.465~W. In contrast, pipelining achieves superior performance, with the 1-round/44-stage architecture delivering 8.96~Gbps throughput and 67.37~Gbps/W energy efficiency, far surpassing loop-unrolled designs (peak 1.88~Gbps, 4.73~Gbps/W). This comprehensive evaluation elucidates critical trade-offs, revealing pipelining's ability to mitigate critical path bottlenecks and optimize energy efficiency. The findings provide FPGA designers with actionable guidance to tailor SIMON 64/128 implementations for IoT applications, such as high-bandwidth sensor networks or low-power RFID tags, advancing lightweight cryptography through precise performance optimization.