Efficient VLSI Design for Real-Time JPEG2000 EBCOT Module with Optimized Codestream Truncation

EBCOT is a critical module in the JPEG2000 image compression algorithm, where the Tier-2 encoding is responsible for optimizing the truncated bitstream to achieve high-quality streams at various compression ratios. This directly impacts key metrics such as image quality at specified compression levels. However, the commonly used Tier-2 module based on the PCRD algorithm suffers from low encoding efficiency and high hardware resource consumption. This paper converts the division and logarithmic operations required by the PCRD algorithm into addition and lookup table calculations. Additionally, it integrates the rate-distortion slope and codeword distribution patterns derived from extensive statistics of images, proposing a VLSI architecture of the Tier-2 module based on a compact lookup table that saves significant resources. Experimental results show that the images compressed by this architecture experience a maximum PSNR decrease of 0.09 dB at low compression ratios and a maximum decrease of 0.29 dB at high compression ratios, with a 4.5\% reduction in the number of encoding cycles. This enhances encoding speed while maintaining encoding quality. Compared to other existing EBCOT architectures, this design achieves a 45\% resource savings on FPGA while reducing area and power consumption by over 77\% in ASIC implementations compared to traditional Tier-2 architectures. The proposed architecture successfully completes high-quality JPEG2000 image compression tasks with lower resource consumption and faster encoding times, meeting real-time requirements.