Semiconductor Wafer Warpage in Electronics Packaging: A Hybrid Investigation with ML and Experimental Insights

Silicon wafers, essential for modern electronics and solar panels, require a thorough understanding of their behavior under thermal stress to ensure reliability in advanced electronics packaging. Warpage, influenced by factors such as material properties, coefficients of thermal expansion (CTE), wafer dimensions, top-layer thickness, and applied thermal profiles, presents a significant challenge in semiconductor manufacturing. This study investigates warpage in silicon oxide-coated wafers of 4-inch, 6-inch, and 8-inch sizes, with thicknesses of 525 µm, 675 µm, and 725 µm, respectively, subjected to a thermal profile peaking at 268°C. Experimental measurements using a laser displacement sensor and reflow oven revealed a progressive increase in warpage with wafer diameter, ranging from 0.3 mm to 0.9 mm. To model and predict wafer warpage, five machine learning (ML) algorithms were applied, with the Rain Forest (RF) algorithm emerging as the most effective. The model was optimized using k-fold validation, shape factor analysis, and heat map evaluation, achieving high accuracy (R² = 0.88) and low mean error. The optimized ML model was validated against experimental data and subsequently employed to predict warpage for a 12-inch wafer, yielding consistent trends. Further comparisons between ML predictions and ANSYS simulations demonstrated that ML predictions exhibited a lower error percentage (5–10%) compared to ANSYS simulations (10–20%), reinforcing the superior predictive capability of machine learning. This study successfully integrates experimental methods and machine learning to address warpage challenges, contributing to advancements in semiconductor manufacturing and electronics packaging.