TestLock: A Testability Logic Locking method against Machine Learning-based Oracle-less attacks

Logic Locking (LL) is a crucial technique for safeguarding Intellectual Property (IP) within the semiconductor supply chain. However, the emergence of sophisticated machine learning-based attacks has posed significant challenges to the security of LL designs. This paper introduces TestLock, a novel LL method that leverages circuit testability metrics to enhance resistance against these advanced threats. By strategically selecting node pairs based on their controllability and observability, TestLock significantly obfuscates the circuit's internal structure, making it considerably more difficult for attackers to identify and exploit vulnerabilities. In the TestLock, we use equivalence class calculations and indistinguishability obfuscation as theoretical proof to formally establish TestLock's resilience, guaranteeing its robustness against machine learning-based attacks. In addition, evaluation against state-of-the-art attacks, including MuxLink and SCOPE, demonstrates TestLock's superior performance in preserving IP integrity. Our results indicate a substantial reduction in attack accuracy, with a 57.13% decrease observed for MuxLink and a 24.22% reduction for SCOPE. TestLock offers a robust and effective defense against these attacks, safeguarding IP from unauthorized access and reverse engineering.