SOT-MRAM-enabled noise-tolerant and resource-saving probabilistic binary neural network

The deployment of large-scale full-precision neural networks is hindered by the escalating parameter sizes and inherent susceptibility to noise. Here, we present a non-volatile memory (NVM)-based probabilistic computing architecture, which harnesses both the stochastic nature and in-memory computing capabilities of NVM to enhance computation efficiency and robustness. Utilizing in-plane magnetized spin-orbit torque magneto-resistive random-access memory (i-SOT MRAM) cells, we demonstrate ultra-fast (400 ps), field-free write operations and voltage-controllable probabilistic states with a low variation of 3.8%. These features enable the implementation of an on-chip SOT probabilistic binary neural network (SOT-PBNN) hardware, achieving near-baseline accuracy (88.2%) on CIFAR-10 classification tasks. Moreover, the stochastic training process endows the SOT-PBNN to attain a 7-fold improvement in classification accuracy over full-precision networks under a 25% write/read noise, while reducing the parameter size by 1–2 orders of magnitude. Our work establishes a lightweight framework suitable for realizing artificial intelligence platforms on resource-constrained edge devices.