Digital Lean Six Sigma Across Vietnam's Electronics-Semiconductor Manufacturing Chain: Longitudinal Evidence from High-Mix Semiconductor-Equipment Contract Manufacturing

Purpose: This study develops and empirically grounds a Digital Lean Six Sigma (D-LSS) architecture for Vietnam's electronics-semiconductor manufacturing ecosystem using longitudinal evidence from a contract manufacturer assembling high-mix semiconductor equipment. The research addresses a practical and methodological gap between increasingly sophisticated DMAIC 4.0 frameworks and the limited plant-level evidence available for high-mix, low-volume semiconductor-equipment assembly in emerging manufacturing locations. Design/methodology/approach: The study reconstructs a longitudinal production event history from 128 production-tracking workbooks covering 111 observed snapshot days from 24 October 2024 to 29 March 2025. After deduplication, 53,860 snapshot-level observations were consolidated into 562 unique units across seven product families. Primary cycle-time inference uses 121 units from four families with exact Start Integration and Final QC dates; schedule-adherence inference uses 140 exact target/Final-QC pairs. Non-parametric tests, bootstrap confidence intervals, robust regression, logistic modeling, and event-history visualization are combined with Lean flow and Six Sigma measurement/control logic. Proprietary identifiers are excluded from the public analytical dataset. Findings: Exact integration-to-Final-QC cycle times differ materially by product family (Kruskal-Wallis H = 37.63, p = 3.39×10^-8). Median cycle time was 4.0 days for Family A (95% bootstrap CI 3–5), 1.0 day for Family B, 1.0 day for Family C and 4.0 days for Family D. Family A and Family C also showed higher observed late-completion proportions (40.0% and 45.7%, respectively) than Family B (12.2%) and Family D (11.1%). Robust log-cycle modeling confirmed strong family effects after accounting for calendar trend and explicit shortage remarks. No monotonic learning trend was detected within the exact-date Family A subset, indicating that the observation window primarily captures post-ramp operational variability rather than a simple learning-curve effect. Practical implications: The empirical results support a plant-ready D-LSS control system built around timestamp integrity, product-family stratification, WIP aging, schedule-risk triggers, material-readiness governance, and standardized milestone definitions. The paper specifies how the same evidence backbone can transfer to SMT and semiconductor back-end environments without treating the CM case as direct evidence for wafer fabrication or OSAT process capability. Originality: The paper contributes a rare longitudinal, auditable dataset and analytical workflow for high-mix semiconductor-equipment contract manufacturing in Vietnam. It moves beyond generic LSS-Industry 4.0 mapping by reconstructing unit-level event histories from operational snapshots, explicitly separating exact from proxy milestone evidence, quantifying product-family heterogeneity, incorporating censoring logic, and linking empirical flow diagnosis to control-oriented D-LSS governance.