Hardware-Hybrid Key-Value Store: FPGA-Accelerated Design for Low-Latency and Congestion-Resilient In-Memory Caching

This paper presents an FPGA-accelerated hybrid architecture for key-value stores (KVS) such as Memcached, designed to overcome latency and congestion challenges that arise in software-based distributed caching systems. By offloading the network and data-index layers to hardware logic within an FPGA, the proposed system reduces context-switch overhead, avoids retransmission-induced congestion loops, and achieves significant power efficiency. Experiments on a Xilinx Zynq-7000 SoC evaluation board demonstrate improved throughput and reduced power consumption compared to conventional kernel-based KVS architectures. This paper outlines the motivation, architecture, experimental results, and implications for scalable, low-latency caching infrastructure.Experiments on a Xilinx Zynq-7000 SoC evaluation board demonstrate improved throughput and reduced power consumption compared to conventional kernel-based KVS architectures. Note: This Technical Note was originally implemented and documented in 2013–2014. It has been revisited and republished in 2025 with updated links and references to preserve technical relevance.