Multi-Line Prefetch Covert Channel with Huge Pages

Modern x86 processors incorporate performance-enhancing features such as prefetching mechanisms, cache coherence protocols, and support for large memory pages (e.g., 2MB huge pages). While these architectural innovations aim to reduce memory access latency, boost throughput, and maintain cache consistency across cores, they can also expose subtle microarchitectural side channels that adversaries may exploit. This study investigates how the combination of prefetching techniques and huge pages can significantly enhance the throughput and accuracy of covert channels in controlled computing environments. Building on prior work that examined the impact of the MESI cache coherence protocol using single-cache-line access without huge pages, our approach expands the attack surface by simultaneously accessing multiple cache lines across all 512 L1 lines under a 2MB huge page configuration. As a result, our 9-bit covert channel achieves a peak throughput of 4,940 KB/s—substantially exceeding previously reported benchmarks. These findings highlight the need for careful consideration and evaluation of security implications of common performance optimizations with respect to their side-channel potential.