Design and Implementation of a Pipelined Software-Defined Fm Receiver on FPGA with Cascaded Decimation and Audio Cleanup Filters

Radio receivers play a crucial role in wireless communication systems, enabling the extraction of information from modulated RF signals. However, traditional analog-based superheterodyne receivers face limitations such as hardware inflexibility, analog drift, frequency instability, and increased design complexity when supporting multiple modulation schemes. These constraints restrict their scalability and adaptability in modern applications. To overcome these issues, this project adopts a fully digital Software-Defined Radio (SDR) approach implemented through FPGA, offering reconfigurability, parallel processing, and support for real-time communication protocols. The proposed SDR receiver design includes a modular architecture composed of SPI-based ADC interfacing, FIFO buffering to manage clock domain mismatches, digital I/Q signal separation using direct digital synthesis and mixing, and cascaded CIC and FIR filters for decimation and spectral shaping. FM demodulation is achieved using a differential multiplier, followed by a low-pass FIR filter to produce clean audio output. Each subsystem was tested independently and later integrated into a full pipeline, with simulation results confirming accurate signal processing and successful audio reconstruction.