A High-Efficiency Frequency Multiplier with Triangular-Resistance Phase Interpolation

A high-efficiency frequency multiplier is presented in 65-nm CMOS with a core area of 0.06 mm2. A low-cost five-segment triangular-resistance phase interpolation scheme is proposed. By performing resistive interpolation on four-path orthogonal triangular signals, 10-fold frequency multiplication is achieved within the input frequency range of 12-20 MHz. The prototype only includes a quadrature square-wave generator, four orthogonal square-triangular converters, and the proposed four-path five-segment triangular-resistance phase interpolators, with the acceptable frequency deviation. The presented design achieves an output power of -9.8 dBm, with an input power of -2.0 dBm and the power consumption of 0.45 mW from a 1.2-V supply, which obtains a frequency multiplication efficiency up to 9.6%. The proposed mechanism could be extended to accomplish a configurable multiplication factor.