A Novel Approach to Semiconductor Fabrication Using Graphene Stencils for Enhanced Nanoscale Lithography

The semiconductor industry is approaching the physical limits of traditional photolithography as device features shrink into the nanometre regime. Although reducing the UV wavelength can, in theory, allow for smaller features, quantum tunnelling and diffraction effects impose fundamental limitations. In this work, we present an innovative fabrication technique that replaces the reliance on ultra-short UV wavelengths with a graphene stencil method. Our process entails sequentially processing a silicon wafer: first depositing a silicon dioxide (SiO₂) layer, then transferring a pre-patterned graphene sheet (carved via focused ion beam or electron beam lithography) onto the SiO₂, and finally depositing a photoresist layer over the graphene stencil. UV exposure then selectively activates the photoresist only in the exposed regions, allowing subsequent etching to define sub-lithographic features. We derive mathematical models—based on the Deal–Grove oxidation kinetics and Rayleigh resolution criteria—to quantify process parameters, and we validate our approach through computational simulations (using FEA and FDTD methods) with data extracted from industry and literature. In addition, we address a critical challenge: the adhesion between the graphene and the SiO₂ layer, proposing solutions such as localized oxide thickness modification and hydrophobic treatment of the graphene underside. Our results indicate that feature sizes as small as 10 nm can be reliably produced, representing a threefold improvement over conventional 193 nm UV lithography. This work provides a detailed roadmap for integrating graphene stencils into semiconductor fabrication using existing technology.